1. Field of the Invention
The present invention relates to a boosting circuit.
2. Description of Related Art
In some boosting circuits, charging and discharging P channel MOS transistors are formed to use an N-type well in a P-type semiconductor substrate or a P-type semiconductor layer as a back gate. In this type of boosting circuit, a parasitic bipolar transistor exists for each of the charging and discharging P channel MOS transistors. Some proposals are made to provide a boosting circuit which can prevent degradation of efficiency due to latch-up and reactive current by preventing the parasitic bipolar transistors of the charging and discharging P channel MOS transistors from being turned on in a boosting operation period during which a boosting capacitor is repeatedly charged and discharged.
However, in transition to an initial charging period during which a boosting capacitor and a smoothing capacitor are charged with an input voltage before start of a boosting operation and to a standby period during which the boosting operation is stopped and the voltages of the boosting capacitor and the smoothing capacitor are decreased to a zero voltage, it is impossible to prevent a base voltage from decreasing lower than an emitter voltage of the parasitic bipolar transistor of each of the charging and discharging P channel MOS transistors. As a result, the parasitic bipolar transistor is disadvantageously turned on to cause efficiency down due to the latch-up and the reactive current. There is a demand for a boosting circuit which can prevent the efficiency down due to the latch-up and the reactive current in the transition to the initial charging period as well as the standby period.
A related art boosting circuit is described in Japanese Patent Application Publication (JP-P2005-45934A). In this boosting circuit, each of charging and discharging P channel MOS transistors has a parasitic bipolar transistor. Hereinafter, this related art boosting circuit will be described with reference to FIGS. 1A, 1B and 2. A basic configuration of the boosting circuit 10 will be described with reference to FIGS. 1A and 1B. The boosting circuit 10 includes a charge pump circuit 11 for boosting an input voltage VIN supplied from an input terminal VDC1 to a twice voltage, a start circuit 12 for initially charging a smoothing capacitor C2 with the input voltage VIN before start of a boosting operation, and a standby circuit 13 for discharging the electric charges stored in a boosting capacitor C1 and a smoothing capacitor C2 to a ground voltage GND.
The charge pump circuit 11 has the boosting capacitor C1, the smoothing capacitor C2, P channel MOS transistors P1 to P6. Q1 shows a parasitic bipolar transistor to the MOS transistor P1. Q2D and Q2S are parasitic bipolar transistors to the MOS transistor P2. Level conversion circuits LS11 and LS21 are level shifter circuits for converting the voltage level of an input logical signal. The level converting circuit LS11 converts an input low level of the voltage GND and an input high level of a voltage VCC into the voltage GND and the voltage VDC1, respectively. The level converting circuit LS21 converts a low level of the voltage GND and a high level of the voltage VCC into the voltage GND and a voltage VDC2, respectively. The MOS transistors P1 and P2 are connected in series, and a source of the MOS transistor P1 and a drain of the MOS transistor P2 are connected to an output terminal VDC2 and the input terminal VDC1, respectively. The boosting capacitor C1 is connected between a node C1M as an output of the level converting circuit LS11 and a node C1P between the MOS transistors P1 and P2. The smoothing capacitor C2 is connected between the output terminal VDC2 and the ground voltage GND.
The MOS transistors P5 and P6 function a switch for connecting a back gate BGP2 of the MOS transistor P2 as a charging MOS transistor to one of a source and a drain of the MOS transistor P2. The MOS transistors P5 and P6 are connected in series in parallel to the MOS transistor P2, and sources of the MOS transistors P5 and P6 are commonly connected, and back gates of the MOS transistors P5 and P6 are connected to the sources, respectively. The MOS transistors P3 and P4 function a switch for connecting a back gate BGP1 of the MOS transistor P1 as a discharging MOS transistor to one of a source and a drain of the MOS transistor P1. Back gates of the MOS transistors P3 and P4 are connected to sources, respectively, and the sources are commonly connected, and the MOS transistors P3 and P4 are connected in series in parallel to the MOS transistor P1. The sources of the MOS transistors P3 and P4 are connected to the back gate BGP1.
Gates of the MOS transistors P1, P4 and P5 are directly connected to an output of the level converting circuit LS21, and gates of the MOS transistors P2, P3 and P6 are connected to the output of the level converting circuit LS21 through an inverter INV21. A clock signal CLK is connected to an input of the level converting circuit LS21 and is connected to an input of the level converting circuit LS11 through an inverter INV11. The MOS transistors P1, P4, P5 and the MOS transistors P2, P3, P6 are complimentarily turned on/off in response to the clock signal CLK.
The start circuit 12 has a P channel MOS transistor P7. Q7 is a parasitic bipolar transistor to the MOS transistor P7. A level converting circuit LS22 converts a voltage level of the input logical signal. The level converting circuit LS22 converts an input low level of the voltage GND and an input high level of the voltage VCC into the voltage GND and the voltage VDC2, respectively. A drain of the MOS transistor P7 is connected to the input terminal VDC1 and a source of the MOS transistor P7 is connected to the output terminal VDC2. The gate of the MOS transistor P7 is connected to an output of the level converting circuit LS22. A start signal STA is connected to the input of the level converting circuit LS22 through an inverter INV12. The MOS transistor P7 is turned on by setting the start signal STA to the high level.
The standby circuit 13 has N channel MOS transistors N1 and N2. A drain of the MOS transistor N1 is connected to the output terminal VDC2 and a source of the MOS transistor N1 is connected to the ground voltage GND. A drain of the MOS transistor N2 is connected to the input terminal VDC1 and a source of the MOS transistor N2 is connected to the ground voltage GND. Gates of the MOS transistors N1 and N2 are connected to a standby signal STBYB through an inverter INV13. The MOS transistors N1 and N2 are turned on by setting the standby signal STBYB to the low level.
The power supply voltage VCC of the inverters INV11, INV12 and INV13 is set to be VCC≦VIN in the boosting operation period. Especially, in case of only an operation in the condition of VCC=VIN during the boosting operation period, the level converting circuit LS11 can be omitted.
A basic operation of the boosting circuit 10 will be described with reference to FIGS. 1A, 1B and 2. The basic operation period includes an initial charging period, a boosting operation period, and a standby period. In the initial charging period, the input voltage VIN is supplied from the input terminal VDC1 and is applied to the boosting capacitor C1 and the smoothing capacitor C2 to initially charge the boosting capacitor C1 and the smoothing capacitor C2 before start of the boosting operation. In the boosting operation period, the input voltage VIN is boosted to twice voltage. In the standby period, the boosting operation stops and electrical charges stored in the boosting capacitor C1 and the smoothing capacitor C2 are discharged to the ground voltage GND. A series of operation period of the boosting circuit 10 is controlled in an order of the standby period, the initial charging period, the boosting operation period and the standby period, as shown in FIG. 2. The input voltage VIN supplied to the input terminal VDC1 is controlled in an outside of the boosting circuit 10 according to a value of the standby signal STBYB. The input voltage VIN is supplied to the input terminal VDC1 when the standby signal STBYB is in the high level, and the input terminal VDC1 is opened (no voltage is supplied) when the standby signal STBYB is in the low level.
First, the boosting operation period will be described. During this period, the start signal STA set to the low level is supplied to the start circuit 12. Accordingly, the MOS transistor P7 is in an off state at all times during the boosting operation period and the input terminal VDC1 is electrically separated from the output terminal VDC2. The standby signal STBYB set to the high level is supplied to the standby circuit 13. Accordingly, the MOS transistors N1 and N2 are in the off state during the boosting operation period, and the input terminal VDC1 and the output terminal VDC2 are electrically separated from the ground voltage GND. When the clock signal CLK of the high level is supplied to the charge pump circuit 11, the output node C1M of the level converting circuit LS11 is in the ground voltage. Also, the MOS transistors P2, P3 and P6 are turned on and the MOS transistors P1, P4 and P5 are turned off. At this time, the input voltage VIN is supplied through the input terminal VDC1 to the boosting capacitor C1. That is, the MOS transistor P2 serves as a charging MOS transistor, and performs a charging operation of the boosting capacitor C1.
Next, when the clock signal CLK of the low level is supplied, the output node C1M of the level converting circuit LS11 is in the voltage VDC1. As a result, the MOS transistors P2, P3 and P6 are turned off and the MOS transistors P1, P4 and P5 are turned on. At this time, the electric charges is discharged from the boosting capacitor C1, and a boosted voltage (=VIN voltage×2) obtained by adding the voltage VDC1 (=voltage VIN) to the charge voltage of the boosting capacitor C1 is outputted from the output terminal VDC2 to charge the smoothing capacitor C2. That is, the MOS transistor P1 serves as a discharging MOS transistor and the level converting circuit LS11 serves as a voltage adding circuit, and a discharging operation of the boosting capacitor C1 is performed along with an adding operation of the power source voltage. By repeating this on/off control, the boosted voltage is outputted to the output terminal VDC2. When an output time of the ground voltage GND from the level converting circuit LS11 and an ON time of the MOS transistor P2 are controlled so that a charge voltage of the boosting capacitor C1 may be saturated, the boosted voltage (=VIN×2) which is twice as high as the input voltage VIN on the input terminal VDC1 is outputted to the output terminal VDC2. When the output time of the ground voltage GND from the level converting circuit LS11 and the ON time of the MOS transistor P2 are controlled so that the charge voltage of the boosting capacitor C1 may be unsaturated, the boosted voltage is lower than a voltage which is twice as high as the voltage VIN (=VIN voltage) of the input terminal VDC1.
Next, operations of the parasitic bipolar transistors Q1 and Q2D during the above-mentioned boosting operation period will be described. In the charging operation of the boosting capacitor C1 in response to the clock signal CLK of the high level, the MOS transistors P2, P3 and P6 are turned on. At this time, the back gate BGP2 of the MOS transistor P2 is connected to the drain (input terminal VDC1) and the back gate BGP1 of the MOS transistor P1 is connected to the source (output terminal VDC2). Thus, the MOS transistor P2 is turned on, while the parasitic bipolar transistor Q2D is not turned on since a base (back gate BGP2) voltage becomes the same as an emitter (input terminal VDC1) voltage. Furthermore, the MOS transistor P3 is turned on, and the back gate BGP1 of the MOS transistor P1 in the OFF state is connected to the source voltage higher than the drain. For this reason, no current flows backward from the smoothing capacitor C2 to the drain of the MOS transistor P1.
Next, the discharging operation of the boosting capacitor C1 will be described. In response to the clock signal CLK of the low level, the MOS transistors P1, P4 and P5 are turned on, and the MOS transistors P2, P3 and P6 are turned off. Also, the back gate of the MOS transistor P2 is connected to the source (node C1P) of the MOS transistor P1 and the back gate BGP1 of the MOS transistor P1 is connected to the drain (node C1P) of the MOS transistor P1. At this time, the MOS transistor P1 is turned on, while the parasitic bipolar transistor Q1 is not turned on since a base (back gate BGP1) voltage becomes the same as an emitter (node C1P) voltage. At this time, the MOS transistor P5 is turned on, and the back gate BGP2 of the MOS transistor P2 in the OFF state is connected to the source of the MOS transistor P2 on a higher voltage side than the drain. For this reason, no current flows backward from the boosting capacitor C1 to a drain side of the MOS transistor P2.
As described above, since the back gate BGP2 of the MOS transistor P2 is connected to the drain so that the base (back gate BGP2) voltage of the parasitic bipolar transistor Q2D may become the same as the emitter (input terminal VDC1) voltage in the charging operation of the boosting capacitor C1 and the back gate BGP1 of the MOS transistor P1 is connected to the drain so that the base (back gate BGP1) voltage of the parasitic bipolar transistor Q1 becomes the same as the emitter (node C1P) voltage in the discharging operation of the boosting capacitor C1, during a boosting operation period of the charge pump circuit 11, the parasitic bipolar transistors Q2D and Q1 are turned on.
Next, the initial charging period will be described. During this period, the start signal STA set to the high level is supplied to the start circuit 12. Accordingly, since the MOS transistor P7 is turned on during the initial charging period to connect the input terminal VDC1 to the output terminal VDC2, the smoothing capacitor C2 is initially charged to the voltage VIN on the input terminal VDC1. The standby signal STBYB set to the high level is supplied to the standby circuit 13. Accordingly, the MOS transistors N1 and N2 are turned off during the initial charging period and the input terminal VDC1 and the output terminal VDC2 are electrically separated from the ground voltage GND. The clock signal CLK set to the high level is supplied to the charge pump circuit 11. The output node C1M of the level converting circuit LS11 is in the ground voltage, the MOS transistors P2, P3 and P6 are turned on, and the MOS transistors P1, P4 and P5 are turned off. Accordingly, during the initial charging period, the boosting capacitor C1 is initially charged to the voltage VIN on the input terminal VDC1.
Next, the standby period will be described. During this period, the start signal STA set to the low level is supplied to the start circuit 12. Accordingly, the MOS transistor P7 is turned off in the standby period and the input terminal VDC1 is electrically separated from the output terminal VDC2. The clock signal CLK set to the high level is supplied to the charge pump circuit 11. The output node C1M of the level converting circuit LS11 is in the ground voltage GND, the MOS transistors P2, P3 and P6 are turned on, and the MOS transistors P1, P4 and P5 are turned off. Since the MOS transistor P2 is turned on during the standby period, the boosting capacitor C1 is connected to the input terminal VDC1. The standby signal STBYB set to the low level is supplied to the standby circuit 13 and the MOS transistors N1 and N2 are turned on during the standby period. Accordingly, the input terminal VDC1 and the output terminal VDC2 are connected to the ground voltage GND, and electrical charges stored in the boosting capacitor C1 and the smoothing capacitor C2 are discharged to the ground voltage GND.
Transition from the standby period to the initial charging period of the related art boosting circuit 10 will be described with reference to FIGS. 1A, 1B and 2. In the transition from the standby period to the initial charging period, when the MOS transistors N1 and N2 are turned off and the input voltage VIN is supplied through the input terminal VDC1 to the boosting circuit 10, the voltage on the input terminal VDC1 starts to rise from the ground voltage GND to the VIN voltage. At this time, the MOS transistor P2, P6, P7, drains of which are connected to the input terminal VDC1, are controlled to be turned on according to the clock signal CLK and the start signal STA during the initial charging period.
However, the voltage VDC1 is equal to the ground voltage GND immediately after start of the initial charging period. Also, the voltage VDC2 is equal to the ground voltage GND immediately after start of the initial charging period. Since level conversion functions of the level converting circuits LS21 and LS22 using the voltage VDC2 as a level conversion power supply voltage cannot be normally performed when the voltage VDC2 is VtP or less, the gate voltages of the MOS transistors P1, P4, P5 and P7 become undefined (voltage lower than [voltage VDC2+VtP]). Furthermore, a logical function of the inverter INV21 using the voltage VDC2 as the power supply voltage is not normally performed when the voltage VDC2 is the threshold voltage VtP or less of the P channel MOS transistor, and the gate voltages of the MOS transistors P2, P3 and P6 are also undefined (voltage lower than [voltage VDC2+VtP]). When the voltage VDC1 is in threshold voltage VtP or less of the P channel MOS transistor, gate voltages of the P channel MOS transistors P2, P6 and P7 are not sufficiently low. Therefore, the MOS transistors P2, P6 and P7 are turned off.
Thus, in start of rising of the voltage of the input terminal VDC1, since the gate voltages of the MOS transistors P2, P6 and P7 are not sufficiently low, the MOS transistors P2, P6 and P7 are turned off (voltage VDC1<VtP: turned off, voltage VDC1=about VtP: turned on with high resistance, a period represented by a dotted line in (h) of FIG. 2). For this reason, the voltage on the node C1P starts rising when the voltage VDC1 rises from [P2 gate voltage+VtP] and the MOS transistor P2 is turned on. Similarly, the voltage of the back gate BGP2 starts rising when the voltage VDC1 rises from [P6 gate voltage+VtP] and the MOS transistor P6 is turned on. Similarly, when the voltage VDC1 rises from [P7 gate voltage+VtP] and the MOS transistor P7 is turned on, the voltage of the output terminal VDC2 rises from the voltage starts. Meanwhile, the MOS transistor P5 is controlled to be logically turned off according to the clock signal CLK during the initial charging period. However, as described above, when the voltage of the output terminal VDC2 is about VtP or less, the gate voltage of the MOS transistor P5 is undefined (voltage lower than [voltage VDC2+VtP]). Thus, when the back gate BGP2 voltage becomes higher than [P5 gate voltage+VtP] and the gate voltage of the MOS transistor P5 becomes sufficiently low, the MOS transistor P5 is turned on (a period represented by a chain line in (j) of FIG. 2).
As described above, when the voltage of the input terminal VDC1 starts rising, any of the MOS transistors P2, P5 and P6 does not normally operate and the MOS transistors P2 and P6 are in the off state (voltage VDC1<VtP: turned off, voltage VDC1=about VtP: turned on with high resistance). Accordingly, it is impossible to prevent the base (back gate BGP2) voltage from falling lower than the emitter (input terminal VDC1) voltage of the parasitic bipolar transistor Q2D. In addition, since the gate voltage of the MOS transistor P5 is undefined, even when the MOS transistor P5 is turned on, it is impossible to prevent the base (back gate BGP2) voltage from falling lower than the emitter (input terminal VDC1) voltage of Q2D.
When the base voltage falls lowers than the threshold voltage of the parasitic bipolar transistor Q2D (generally, threshold voltage VBE of the bipolar transistor, VBE=about 0.7 V), the parasitic bipolar transistor Q2D is turned on. Meanwhile, since the MOS transistor P7 is also turned on (voltage VDC1=VtP or less: turned off, about VtP: turned on with high resistance), the parasitic bipolar transistor Q7 cannot prevent the base (output terminal VDC2) voltage from falling lower than the emitter (input terminal VDC1) voltage. When the base voltage falls lower than the threshold voltage VBE of the parasitic bipolar transistor Q7, the parasitic bipolar transistor Q7 is turned on. In this manner, in the related art boosting circuit 10, in transition from the standby period to the initial charging period, it is impossible to prevent the base voltage from falling lower than the emitter voltage of the parasitic bipolar transistors Q2D and Q7. Since the parasitic bipolar transistors Q2D and Q7 are turned on, the reactive current and the latch-up disadvantageously occur during the initial charging period.
Next, a transition from the boosting operation period to the standby period in the related art boosting circuit 10 will be described. In the transition from the boosting operation period to the standby period, electrical charges stored in the capacitors C1 and C2 are discharged to the ground voltage GND.
First, a case will be described that there is a period during which a discharge time of the smoothing capacitor C2 is shorter than that of the boosting capacitor C1 so that the voltage VDC2 becomes lower than the voltage VDC1 and a node C1P voltage (for example, C1>C2). When the voltage VDC2 becomes lower than the voltage VDC1, the base (output terminal VDC2) voltage becomes lower than the emitter (input terminal VDC1) voltage of the parasitic bipolar transistor Q7. At this time, when the base voltage falls lower than the threshold voltage VBE of the parasitic bipolar transistor Q7, the parasitic bipolar transistor Q7 is turned on.
The MOS transistor P3 is controlled to be logically turned on in response to the clock signal CLK during the standby period, and the ground voltage GND is supplied to the gate of the MOS transistor P3. Thus, the output terminal VDC2 is electrically connected to the back gate BGP1. When the voltage VDC2 is lower than the node C1P voltage, the base (back gate BGP1) voltage falls lower than the emitter (node C1P) voltage of the parasitic bipolar transistor Q1, following the voltage VDC2. When the base voltage decreases lower the threshold voltage VBE of the parasitic bipolar transistor Q1, the parasitic bipolar transistor Q1 is turned on.
Next, a case will be described that a discharge time of the smoothing capacitor C2 is slower than that of the boosting capacitor C1 and the voltage VDC2 is not lower than the voltage VDC1 and the node C1P voltage (for example, C1<C2). The MOS transistors P2 and P6 are controlled to be logically turned on according to the clock signal CLK during the standby period, and the ground voltage GND is supplied to the gate of the MOS transistors P2 and P6. Thus, the input terminal VDC1 is electrically connected to the back gate BGP2. When the voltage VDC1 is lower than the node C1P voltage, the base (back gate BGP2) voltage (=voltage VDC1) decreases lower than the emitter (node C1P) voltage of the parasitic bipolar transistor Q2S. Then, when the base voltage decreases lower than VBE of the parasitic bipolar transistor Q2S, the parasitic bipolar transistor Q2S is turned on.
As described above, in the related art boosting circuit 10, in transition from the boosting operation period to the standby period, it is impossible to prevent the base voltage from decreasing lower than the emitter voltages of the parasitic bipolar transistors Q1, Q2S and Q7. As shown in FIG. 2, when a discharge rate of the smoothing capacitor C2 is high, the parasitic bipolar transistors Q1 and Q7 are turned on. As shown in FIG. 3, when the discharge rate of the smoothing capacitor C2 is low, the parasitic bipolar transistor Q2S is turned on. Thus, in transition from the boosting operation period to the standby period, the reactive current and the latch-up may occur disadvantageously.